v0.1 · AXI-Lite available now

Generate production UVM testbenches in seconds.

Describe your bus interface. Get a complete, multi-file UVM project — agent, sequences, environment, scoreboard, tests. Ready to drop into your repo and compile.

Start generating Read the SystemVerilog notes

Free forever No account required MIT licensed output

axi_lite_driver.sv

class axi_lite_driver extends uvm_driver#(axi_lite_seq_item);
  `uvm_component_utils(axi_lite_driver)

  virtual axi_lite_if vif;

  task run_phase(uvm_phase phase);
    forever begin
      seq_item_port.get_next_item(req);
      drive_transfer(req);
      seq_item_port.item_done();
    end
  endtask
endclass

UVM testbench generator

claude opus 4.7

Address Width bits

Data Width bits

DUT Name snake_case

Agent Role

Include

Scoreboard Coverage SVA assertions UVM reg model Error injection

Additional Notes optional

How it works

Three steps, no setup required.

Every generation is shaped by a system prompt built from years of production verification work. Not textbook UVM — the kind that ships.

Configure

Pick your protocol, set the widths, choose which features you want. Add any DUT-specific notes.

Generate

Claude writes a complete, multi-file UVM project tailored to your specification. Takes about 30–60 seconds.

Download

Grab the zip, drop it into your repo, compile on VCS, Xcelium or Questa. Iterate by regenerating.

About

Built by a verification engineer.

asicverif.ai is a small project by a Senior Design Verification engineer with 13+ years at tier-one silicon companies — PCIe, NVMe, security IPs.

The scaffolding of a UVM testbench is essentially the same every time, only the details change. This tool takes care of the boilerplate so you can focus on the details that matter — coverage models, protocol corner cases, the specific quirks of your DUT.

The service is free. If it saves you an afternoon, buy a coffee. No accounts, no upsells, no tracking.