Describe your bus interface. Get a complete, multi-file UVM project — agent, sequences, environment, scoreboard, tests. Ready to drop into your repo and compile.
Every generation is shaped by a system prompt built from years of production verification work. Not textbook UVM — the kind that ships.
Pick your protocol, set the widths, choose which features you want. Add any DUT-specific notes.
Claude writes a complete, multi-file UVM project tailored to your specification. Takes about 30–60 seconds.
Grab the zip, drop it into your repo, compile on VCS, Xcelium or Questa. Iterate by regenerating.
asicverif.ai is a small project by a Senior Design Verification engineer with 13+ years at tier-one silicon companies — PCIe, NVMe, security IPs.
The scaffolding of a UVM testbench is essentially the same every time, only the details change. This tool takes care of the boilerplate so you can focus on the details that matter — coverage models, protocol corner cases, the specific quirks of your DUT.
The service is free. If it saves you an afternoon, buy a coffee. No accounts, no upsells, no tracking.